Re: Rep:[f-cpu] about the scheduler...

[jaap stolk <jwstolk@yahoo.com>]

--- Nicolas Boulay <nicolas.boulay@ifrance.com> wrote:
> -----Message d'origine-----
> De: Yann Guidon <whygee@f-cpu.org>
> A: fm <f-cpu@seul.org>
> Date: 02/08/02
> Objet: [f-cpu] about the scheduler...
> 
> hi !
> 
> Jaap made a drawing :
> http://f-cpu.seul.org/~f-cpu/new/scheduler.png
> 
> This does not take into account the problem of the
> 3r1W
> cases (or 2R2W, depends), where the 4rth register
> number
> is this of the 3rd field with the LSB inverted.
> There must be a comparison with this negated bit,
> but fortunately it is easier to write it in VHDL
> than explain it by email :-)
> 
> Otherwise, the drawing looks more complex than it
> is,
> it's just some FF, MUX and comparators that are
> copy/pasted
> and the basic principle is there.
> 
> >>> "just" some muxes ? :p but i always don't
> understand why you need a
> specific unit to do it and not displaced the task to
> each unit.
> 
the ragister nr queue needs to be checked for posible
stalls, it would be to slow if we need to get all
this info to and from each EU.
the write port nr queue only controls the xbar write
and the register write, as the register unit is
a bit sloow, it would be nice to put the queue close
to that.
if there is going to be an "enable" FIFO that travels
along each EU, we can't realy use that in the
scheduler
unles its phisicaly neer the scheduler.

i changed my mind on this:
the check for zero in the register write queue can
be don in other ways, like just ignoring
R0_busy when R0_nr == 0.

but we still need to check somehow if a write slot is
free.

if we write to R0, then it would nice if we
kept the write (port nr) out of the queue, so we
can use that write slot for somthing else.

> >>> To do the scoreboard stuff, a memory could be
> used but it's could
> not be the fastest design possible.
> nicO

as far as i can see, if we use a scoreboard to get the
condition flags for a register, we still need to
bypass
it in the x-bar stage, so why not always do it in the
x-bar stage ? (the condition register can be read
onto the x-bar read bus, and in case of a bypass
the register valueue end op on the x-bar anyway.

> 
> WHYGEE
>
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