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Re: [f-cpu] about the scheduler...



hi,

--- Yann Guidon <whygee@f-cpu.org> wrote:
> hi !
> 
> This does not take into account the problem of the
> 3r1W
> cases (or 2R2W, depends), where the 4rth register
> number
> is this of the 3rd field with the LSB inverted.
> There must be a comparison with this negated bit,
> but fortunately it is easier to write it in VHDL
> than explain it by email :-)

ah, i think i get your point now, as far as i
can see, its ok to write to a register that is
"being computed" as long as the second write will
be performed _after_ the first one. xmp:

add r1,r2,r3 (2 cycle)
mov    r4,r5 ( 0 cycle)

the simulator now wtites r4 first and r1+r2 later
and the resulting value in r3 is wrong. :-(
and than we have situations like these

add r1,r2,r3 (2 cycle) (don't write carry)
nop
mov    r4,r3 ( 0 cycle)

where both write ports try to write to r3 at the same
time. 

thanks,

jaap.



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