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[f-cpu] ASIC vs FPGA vs Emulation vs simulation



hi,

i was browsing comp.dsp when i found the following post.
The author seems to mix FPGA and emulation
(FPGA are not used /only/ for emulation) but
he raises quite some interesting points, hence i copy it here :

~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

In article <ANt2b.264953$Ny5.8149096@twister2.libero.it>,
ArnoldZQW@NOSPAM.aol.com (Arnold Z.) wrote:


Hi all,

I need to prototype some ASIC designs and I'm looking for
advice on type of FPGA and on FPGA board as well (to buy one
or alternatively to make one on my own).

The FPGA should be capable of the equivalent of about 100K
to 500K ASIC logic gates (being 300K a good estimate).
But this is the least important point, since every family of
FPGAs comes in various gate counts.
What I really care most is to choose the right FPGA family
since the start.

Clock speed is not critically important, but it should not
be lower than 50 MHz anyway.

I'd like to match the FPGA design to the ASIC one as closely
as possible, so I'm ruling out any FPGA that for its performance
depends too much on some "original features".
Sure, I don't pretend a FPGA with only 2-inputs NAND gates per
cell and millions of freely routable cells.. but something as
close as possible to an ASIC, because it will all end up on a
ASIC anyway sooner or later, and I don't want the FPGA and the
ASIC to be too much different each other, so to force me to
find completely different solutions. I can sacrifice FPGA speed,
but not to an extreme point. Hence, I'm looking for the most
"ASIC-like" FPGA.

[snip]

Now the sad part: I am on very low budget. This is a hobbyst
project for me, but I think I have a very innovative and valid
design in mind. I do not want to be ripped off, so I want to try
it myself. I will enjoy doing so anyway, and time is not a big
problem (I have some free time to invest on it). I have no
digital electronics degree, although I'd say I'm very, very
experienced assembly programmer (various 8..64 bit CPU's, DSPs
and microcontrollers) and with a long experience in digital
electronics as a self taught hobbist (no previous FPGA direct
experience though!).
As I said I've some rather interesting/innovative/original
design/concept to develop and test, and the only viable way
will be a FPGA. But which one? You certainly know much better
than me!

Once the design, on the FPGA, should prove its validity, I'd
move on to look for investors and some ASIC engineer for the
real thing.


I have a bit of experience here. We are on our third ASIC emulation. The first two were FPGA-based and used Xilinx Virtex-II parts. Currently, we are using a commercial ASIC emulator (Axis).

If I had the time I could write pages on why FPGA-based emulation is a waste of time. Unfortunately, due to the shortcomings of our prior emulations, we are behind schedule so instead you get a summary...

Bottom line: based on my experience, I would say don't bother with the FPGA-based emulation. Your time and money will be better spent on simulations.

Other:

1) The VHDL is not compatible. We had to completely rewrite ours.

2) The libraries are different and not compatible.

3) No matter what, you'll end up optimizing (size and/or speed) for the FPGA. Those optimizations will further hinder re-use.

4) Emulated clock speed is more like 2 MHz (FPGAs are great for point designs but not for emulation).

That's all for now,

Ken P.


~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

curiously, this answer was posted on comp.dsp but i have no idea
where the original post was (i haven't seen it on comp.dsp).
maybe the answer was posted on the wrong group.

Now, the "The VHDL is not compatible." argument is a critical
point for F-CPU. If it gets implemented in one FPGA,
one has to rewrite a good share of code. This would be a "fork"
from the original source, but they have to be kept in synch anyway,
or else advances in any branch will be useless for the others.
And if another brand of FPGA gets used, this becomes another fork.

Now (or more precisely, since a few years) F-CPU development faces a
big problem :
- either we concentrate on "portable-only code" that is useful
only for high-level simulation (everybody can use it but it's slow)
and synthesis (almost nobody can use it),
- or we decide to implement some code in FPGA, thus jeopardizing
portability and dropping "Freedom" from the project names, just
so early physical implementations can be used for hacking.

I'm among those who would like to try to put F-CPU code in
FPGA, as i am getting fed up of doing "virtual things" only.
But then, it is possible only if we could get our hands on
one FPGA board from all major manufacturers, or else our
code would depend on the whims of only one of them.

YG

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