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Re: [f-cpu] F-CPU architecture...

Yann Guidon wrote:
Tobias Bergmann wrote:
Yann Guidon wrote:

Hi Yann,

it puts some constraints on the LFSR algo but
it makes it more challenging and interesting :-)

You mean Reseeding?
I work on dynamic reseeding atm. Maybe something can be reused for the F-CPU.

Well your power supply has to be dimensioned for this worst case as well. Makes it more expensive for no good reason.
hmmm not sure.
we'll have to "measure" the average and max activity ...

Usually power during random test is approx 4x the power in system mode at same freq.
But the ratio depends on whether you look at a low power design or high performance design. So we have to obtain it for F-CPU.

i had thought about defining our own VHDL data types
(instead of std_logic) so we can implement our own coverage tools.
It can also serve to create stats about activity etc...
but that would be very heavy and may not remain acurate
when we implement the core in ASIC or FPGA.
sometimes, synthesis can radically change the netlist and the low-level

If I'm not mistaken then SIGNS gets that functionality soon or already has it.
No need to spend precious F-CPU-time on it.

Oh I forgot to mention: A collegue of mine is writing a OS tool for circuit simulation, synthesis, ATPG, fault sim, ...
It's called signs: http://www.iti.uni-stuttgart.de/~bartscgr/signs/wiki/index.php/Main_Page

I'm not rich but I have quite nice FPGAs at work.
such as ? :-)

A couple of prototype boards with Virtex-something and an Emu-machine with 3 large FPGAs.
I don't synthesize usually so I don't care much about exact size/speed/etc. But I can have a look. And I know we ordered a bigger one for next year.
What I remember is that we can handle designs of approx 10MGates.

that is the best point to start. x86 proves that we can always scale up
and the F-CPU model has some headroom.

scalability is good.
How large would the effort be to add SMT to the FC0 core? I'm thinking of approx. 3-fold SMT.

The way i "solve" the memory bandwidth problem is by going
"multichip" (coherent NUMA) instead of "multicore".

As long as we put the available transistors on a die to good use. :-)

bis besser,
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