Re: [f-cpu] register set

[Ben Franchuk <bfranchuk@jetnet.ab.ca>]

Kim Enkovaara wrote:
> 
> > I have based the design on transparent latches,
> > they ensure that the cells are not too large and slow.
> > It's almost completely asynchronous : reading is just
> > combinational (the address is driven by the fetcher's
> 
> Have you tought about test structures for ASIC manufacturing? Latches are
> never fun thing to test. D-flipflops are so much easier to test with
> normal scan paths.
How ever Latches are 1/2 the size of flip-flops.I like latches as data
flows through them but flip-flops stop the data flow until a good bit
after the clock. Regardless scan paths are hard to test and design as
your scan logic messes up your data logic.
-- 
Ben Franchuk - Dawn * 12/24 bit cpu *
www.jetnet.ab.ca/users/bfranchuk/index.html
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