[f-cpu] SIMD and exception

["gaetan@xeberon.net" <gaetan@xeberon.net>]

Hello F-World

Two other questions today :)
1) i'm thinking my current way to handle SIMD will not be correct. For 
the moment, in each stage, i check if i do operations in 32 bit or in 
64bit. The problem is it's add a MUXto each stage... and it's at lease 2 
gate deep.
In fact i do in each stage:
if (OpSize = single) then
 make operation op1 with operands as single float
else -- opsize = double
 make operation op1' with operands as double
end if;
and the comparison are with 2 bit vector (00=32bit, 01=double), so it's 
huge for each stage...

So i think to other methods:
- select in the good way in the first stage (with a decoder, to prevent 
unused path to switch transistors), and select the good result in the 
last stage. The problem is it will use twice more component (for 
instance i use only one 64 bit generic_adder for both SIMD format, but 
now i will to do addition for single and an other addition for double 
float). It will also add twice more registers. The problem here is the area.
- to convert everything in 64 bit and do all operation in 64 bit (i 
think this is how the pentium works), BUT the problem is in the last 
stage, i will have to cut the mantissa and exponent, and this will add 
some logic, so increase the number of stage by at lease one (especialy 
for the rounding step)
For the moment, i think everything should fit into 4 cycle, but some 
problem can occurs, so it may use 5 cycles at the end.
So i would like to know what do you think about that.

2) I manage exception with an exception flag, so when an exception 
occurs (ex: when and operand is +infty), i just propagate this exception 
to the last stage and it will output the exception flag with a correct 
output (Dout_0(64 downto 0) = NaN, +/-infty/...). But is it that in all 
case ? In fact, i don't really see what i should do when the ieee flag 
is set or not. Should i stop the pipeline and output now (so i need to 
add an ouput bit saying '"i'm putting something in the output"... I 
mean, everything will be done by the fetcher (stop the feeding the 
pipeline,...). Or is that when the flag is set, i don't ouput any 
exception (but i still output NaN, +/- infty?? or default number (like 0)).


Seems like there is a long path before me to understand everything in 
this Funny-World...

--

~~ Gaetan ~~
http://www.xeberon.net


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