Re: [f-cpu] Re: Delay

[Nicolas Boulay <nico@seul.org>]

Le Lundi 9 Février 2004 23:18, Yann Guidon a écrit :
> good evening,
>
> Nicolas Boulay wrote:
> >Le Lundi 9 Février 2004 21:36, Michael Riepe a écrit :
> ><...>
> >
> >>which takes 3 inverters and an and-or-invert (AOI) gate, resulting in
> >>d=2/t=2. But on the other hand, you wrote "xor", so the synthesizer may
> >>create just that.
> >>
> >>I suggest you use work.misc.xor3 (available for both std_ulogic and
> >>std_ulogic_vector) if you need a 3-input XOR. It's easier to adapt a
> >>single function to the target than to scan the whole F-CPU for stray
> >>3-input XORs.
> >>
> >>On the other hand, if you *know* that one of the inputs arrives late,
> >>you can as well use
> >>
> >>	Y := (A xor B) xor C;	-- when C arrives late
> >
> >It's much better to write "A xor B xor C". Synthetiseur are really good to
> >balance tree of signal's, if you write something else you over constraint
> > it.
> >
> >If you use and/or/not gate, it will hardly find the away to use the xor
> > gate if available. But from the "xor" statement it will find the better
> > way to produice a xor without a xor cells.
> >
> >We should code at the highest level as possible, most of the time, the
> >synthetiseurs will more clever than us. And it will adapt the better code
> > for the technology available which is impossible to do by hand.
>
> I agree with what you say.
> The real question is now : how can we evaluate the (relative) delay ?
>
> We are currently only speaking about boolean logic.
> Then will come the time where wires/buses and memory arrays
> will play a significant part, so the question is increasingly critical.
>

The recommendation is to put flipflop at the end of each entity, tools as 
synopsys respect boundaries, so it could optimise some logic by using JK 
cells. 

But we could also define input flipflop. It will add a pipestage, but it will 
be easier to place the unit on the die. You will have the famous "routing" 
pipestage.

Maybe each "Big" unit could have this registred input. Maybe also a group of 
smaller one, too.

The only way to comparre unit, is to synthetise it and each unit must reach 
the same speed. If not, you could also use option like "balanced register" 
that put some logic in the "other side" to increase clock speed (with this 
option, LEON became 20% bigger and 10% faster). 

nicO

> >nicO
>
> YG
>
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