Re: [f-cpu] Re: Delay

[nico@seul.org]

> Moin!
>
> Yann Guidon wrote:
>> good evening,
>>
>> Nicolas Boulay wrote:
> [...]
>>> It's much better to write "A xor B xor C". Synthetiseur are really
>>> good to balance tree of signal's, if you write something else you over
>>> constraint it.
>>>
>>> If you use and/or/not gate, it will hardly find the away to use the
>>> xor gate if available. But from the "xor" statement it will find the
>>> better way to produice a xor without a xor cells.
>
> Synthesizers are like C compilers. I don't trust the latter, so why
> should I trust the former? After all, C compilers are much more
> elaborated. But they still can't find optimal translations in many cases.
>

VHDL synthetiseurs are much more elaborated than C compiler. They need
internal static analisys to find worst path, they balanced between speed
and area constraint and now power consumption. Synthetiseur like simplify
try to recognise FSM and data path. They could also balanced register,
create tree to deal with late arriving signals... All the kind of stuff
very time consuming to be optimised by hand for a given technology.

>>> We should code at the highest level as possible, most of the time, the
>>> synthetiseurs will more clever than us. And it will adapt the better
>>> code for the technology available which is impossible to do by hand.
>
> Well, if synthesizers were as clever as you say, we could feed the F-CPU
> manual into them and they would do the rest.
>

Sur, but the f-cpu manual aren't written in synthetisable VHDL :)

>> I agree with what you say.
>
> Thank you ;-)
> SCNR.
>
>> The real question is now : how can we evaluate the (relative) delay ?
>
> In general: not at all.
>

The only way is to synthetise the code and see the result.

nicO

> Michael.

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