Re: [f-cpu] fadder forever

["gaetan@xeberon.net" <gaetan@xeberon.net>]

hello
i'm starting the next 2 stages description and had no feedback from the 
F-team about my schematic :|, i hope it means "it's ok".
It especially about the delay pbl, i don't know if i handle it 
correctly... you know, if there is a mistake somewhere it
will "shift" everything...:(

gaetan@xeberon.net a écrit :

> Hello F-boyz!
>
> I'm still trying to include everything everyone told me in my work, 
> and i'have drawn a figure with *everything* i will add (if it's not 
> already existing).
> For the moment i only have the two first stage, but you will see how i 
> handle the work (i hope because it's a heavy schematic)...
> I tried to respect the 6 gates delay limit the better i can.
> If you want a more readable figure, i can draw another one.
> The principe is the one described in the "rounding ... using a 
> compound adder" paper (url: 
> http://citeseer.nj.nec.com/bruguera98rounding.html), but with SIMD 
> handling...
> The other stage will follow the same scheme.
>
> so, you can see if something will not work...
>
> byebye
--

~~ Gaetan ~~
http://www.xeberon.net


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