Re: [f-cpu] latest gcc & immediate addressing [Was: BOUNCE f-cpu@seul.org:...](fwd)

[Yann Guidon <whygee@f-cpu.org>]

hi !

Michael Riepe wrote:

> On Wed, Jan 08, 2003 at 03:01:32AM +0100, Yann Guidon wrote:
> [...]
>  
> > As far as i remember, the ROP2 instructions follow the general rule :
> > the "size" field indicates the number of bits to write back.
> > That is : one can do a OR on one byte or word, and the rest will
> > be cleared.
> >    
> Very good. Then I'll have to change my instruction encoder/decoder.
> What about the `full-size' operation?
>  
it's done with the SIMD flag.

> > Then comes the problem of the chunk size of the COMBINE mode,
> > it requires 2 more bits which are taken from the IMM mode
> > so only the register form is possible when combine is needed (IIRC).
> >    
> Is it useful to separate operation and combine chunk sizes? I'd rather
> use the standard scheme (size + SIMD flag).
>  
what if you want to compare and combine 2 16-bit chunks in parallel ?

in the conference, i gave an example code that compares 4 bytes in parallel,
so there are only 32 useful bits.

> [...]
>  
> > ROP2 :
> > 27-31 : Opcode
> > 24-26 : function
> > 22-23 : size flags (normal ones)
> > 20-21 : Combine size flags (not used yet, only 00 is used for bytes)
> >    
> This is new to me. When did you change it?
>  
i guess it is quite old, maybe 16 months (when i was staying at Graham's 
place).
it can probably be traced by looking in old snapshots....

> [...]
>  
YG

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