Re: [f-cpu] latest gcc & immediate addressing [Was: BOUNCE f-cpu@seul.org:...] (fwd)

[Michael Riepe <michael@stud.uni-hannover.de>]

On Wed, Jan 08, 2003 at 03:01:32AM +0100, Yann Guidon wrote:
[...]
> As far as i remember, the ROP2 instructions follow the general rule :
> the "size" field indicates the number of bits to write back.
> That is : one can do a OR on one byte or word, and the rest will
> be cleared.

Very good. Then I'll have to change my instruction encoder/decoder.
What about the `full-size' operation?

> Then comes the problem of the chunk size of the COMBINE mode,
> it requires 2 more bits which are taken from the IMM mode
> so only the register form is possible when combine is needed (IIRC).

Is it useful to separate operation and combine chunk sizes? I'd rather
use the standard scheme (size + SIMD flag).

[...]
> ROP2 :
> 27-31 : Opcode
> 24-26 : function
> 22-23 : size flags (normal ones)
> 20-21 : Combine size flags (not used yet, only 00 is used for bytes)

This is new to me. When did you change it?

[...]
-- 
 Michael "Tired" Riepe <Michael.Riepe@stud.uni-hannover.de>
 "All I wanna do is have a little fun before I die"
*************************************************************
To unsubscribe, send an e-mail to majordomo@seul.org with
unsubscribe f-cpu       in the body. http://f-cpu.seul.org/