Re: [f-cpu] (next) crazy idea about immediates

[devik <devik@cdi.cz>]

> > All data needs to be aligned. Ok. We can also suggest
> > aligning structures to cacheline boundary (and malloc
> > would return such aligned pointers).
>
> That may cause a lot of internal fragmentation.

hmm it is possible unless you take care of it. where you
can use it without too many problems are string operation
where you pre-align address at start, in function prologs
where we know local stack size and can optimize its size
and placement. I agree that it is not simple.

> > We could support load/store with 5bit immediate value
> > which would be ORed with physical address in register.
>
> Umh... yet another load/store instruction?

:-] yes

>
> > This way there is no need to change LSU working, no
> > other pipeline stage, no problems with exceptions.
>
> You'll have to check for correct alignment.

I don't think so - it would be programmer's/compiler's job
to use it at appropriate places. I see it as direct addressing
of single cacheline.
I hope you agree with me that implementation is easy. And
we both know that compiler design would be more tough with
this in mind - but not impossible.
But well, only simulating it can prove whether it is worth
of any work. In any case it is very fast indexing and can
save us trubles with more pointers pointing single cacheline.
Also this way you could schedule 4 loads (if we'd have 4 LSU)
in paralel with single pointer ....
devik


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