Re: [f-cpu] (next) crazy idea about immediates

[Yann Guidon <whygee@f-cpu.org>]

hi,

Michael Riepe wrote:

> On Wed, Jan 08, 2003 at 12:31:56PM +0100, devik wrote:
>
> > during night I got other crazy idea - but interesting.
> > All data needs to be aligned. Ok. We can also suggest
> > aligning structures to cacheline boundary (and malloc
> > would return such aligned pointers).
> >    
> That may cause a lot of internal fragmentation.
>  
> > We could support load/store with 5bit immediate value
> > which would be ORed with physical address in register.
> >    
> Umh... yet another load/store instruction?
>  
looks so.

> > This way there is no need to change LSU working, no
> > other pipeline stage, no problems with exceptions.
> >    
> You'll have to check for correct alignment.
>
> [...]
from the hardware point of view, the 5 bits immediate that is ORed has few
potential problems, excepts that it is only useful for "small integers"
(using 64-bit data reduces the usefulness to 2 bits) and alignment must
be taken into account (here, the same policy can be used : the LSB of the
constant can be cleared, or a trap is triggered if an error condition is 
detected).

The pointer's LSBs are already checked for the normal LSU operations,
but another condition would be checked : if the LSB AND the IMM5 give
at least a "1" bit. this can be used on purpose but usually it means some
kind of misalignment or overflow.

Another solution that increase the efficiency of the 5-bit immediate
would be to shit the imm5 according to the data size, but here there
are risks of going out of the cache line, which makes things too complex
for the current LSU.

I can see no serious objection to this instruction, even if it does not 
follow
the logic behind the LSU principle, but the reduced range of 5 bits makes it
possible. Then, the exact behaviour about alignment must be defined
but it should be ok.

YG

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