Mload and Rep:[f-cpu] Problem with load/store size flags on >64bit F-CPU

["Nicolas Boulay" <nicolas.boulay@ifrance.com>]

Soon the same mistake !

256 bits register means 4*64, 8*32, 16*16, 32*8 bits data words. (That's
why we need more inter-chunk operation.)

So the SIMD load will load 256 bits at a time, the scalar one only the
asked size (which is a pain that current risc processor didn't do).

256 bits is a great number because it's 4*64 double which is a good
compromised for a lot of scientifique code.

The simplest mload could be a load of 4 registers at a time with an
aligned memory boundary (no heavy and slow shift). So you could
load/store Reg0-3, Reg4-7,... in the same time with a complete cache
line (1024 bit :D), that's why the pointer must be aligned. 

It's very simple to do it in hardware. It simplify the register access
by using a 16*1024 bits register bank (quicker than a 64*... ) then you
use a mux for choosing narrower data. It could be also an easy means to
pipeline register access (2 stages in that case).

nicO

-----Message d'origine-----
De: devik <devik@cdi.cz>
A: <f-cpu@seul.org>
Date: 10/01/03
Objet: [f-cpu] Problem with load/store size flags on >64bit F-CPU

Hi,

assume you have 256bit cpu. Then you certainly want to
load whole register at once (whole cache line :))).

But as there was already said we don't need (or want to
implement) more that 64bit chunk size.
But then when one sets size flags to 8/16/32/64 bits
(which is very useful combination imho) he can't do it.
When is sets 8/16/32/256 he can't use 256 for other than
LSU ops.
Would not be better to have separate SRs for LSU so that
they use different size meaning ?

devik

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