Re: [f-cpu] Free synthesis tool for Verilog and other links

[Michael Riepe <michael@stud.uni-hannover.de>]

On Thu, Jul 18, 2002 at 06:34:48PM +0200, Yann Guidon wrote:
[...]
> However, VHDL allows you to replace one version of a module ("entity" in
> VHDL jargon) with another version ("architecture" in VHDL, which can be
> written differently or even include a technology-specific description
> (hierarchical or flat netlist for example).

The question is whether such an architecture can still be considered
`edible source code' or whether it is `binary'. Imagine someone who
takes the original source, creates an optimized netlist from it and then
edits it... that's almost like bit-twiddling in .o files.

-- 
 Michael "Tired" Riepe <Michael.Riepe@stud.uni-hannover.de>
 "All I wanna do is have a little fun before I die"
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