Re: [f-cpu] Free synthesis tool for Verilog and other links

[Ben Franchuk <bfranchuk@jetnet.ab.ca>]

Just an Illusion wrote:

> The h/w exchange format are hdl (vhdl and verilog) sources, hdl netlist 
> source and *edif* format. See the different h/w project on the net.


There is some good stuff out there but good I/O devices are still harder
to find Open Source. A whole lot 6502 chips with out BCD math too.

Since I will be designing in TTL for a while still all my source is
in PDF schematics :)


> Wait, wait, don't make mistake.
> The both main hdl language are *not* fpga specific.

It is the minor ones -- Cupl,Ahdl,Pal-asm I was thinking about.

> The both ones are h/w modelisation language to design any h/w systems 
> (digital or not, with the vhdl-ams and the verilog-a extension). The 
> design can be implemented (fully or partially) in any type of 
> appropriate programmable logic like : rom, prom, eprom e2prom, ram, pld, 
> gal, fpga, asic...

I note TTL is missing from the LIST (grin).

> 
> Search the processor Mark2 code, this is an old model of 8 bit processor 
> given into the book :
> R. ARMSTRONG : Chip-Level Modeling With VHDL; Prentice Hall, Englewood 
> Cliffs,NEW-JERSEY 07632. 1989
> 
> And try to synthesize the code, or try to rewrite it like rtl model and 
> you can see the difference.

I live in the middle of the Great White North of Canada, getting any book
is difficult unless I buy it. I would like to learn a HDL but I need a
book that explains the languge and constructs well rather than teaching
logic. A complier would help too, but this thread is getting off topic now.

-- 
Ben Franchuk - Dawn * 12/24 bit cpu *
www.jetnet.ab.ca/users/bfranchuk/index.html

*************************************************************
To unsubscribe, send an e-mail to majordomo@seul.org with
unsubscribe f-cpu       in the body. http://f-cpu.seul.org/