Re: [f-cpu] MUL question

[Michael Riepe <michael@stud.uni-hannover.de>]

On Sat, Jul 27, 2002 at 06:03:40AM -0700, jaap stolk wrote:
> 
> the manual is not very clear on the latency of
> the MUL EU.
> from the VHDL i understand it's like:
> 
>  size:  reult(low) result(high)
>  8 bit      3          4
> 16 bit      4          5
> 32 bit      5          5
> 64 bit      6          6

Correct.

> my question is, (even if the actual numbers change)
> are we going to have seperate latencies for each
> output ?

In most units, no. In this unit, yes.

> and what if the used write slots look like this:
> (i know a very big if)
> w0    w1
> used used
> free free
> used used
> free free
> used used
> free free
> used used
> 
> we would never be able to start the MUL, unles we
> delay one of the MUL EU outputs to pull it strait.
> (of corce this also hapens the other way around,
> when none of the write slots are aligned, and we
> need two aligned slots (like ADD+carry))

I guess that's an Xbar question.

> do we delay one of the outputs, or just wait for
> a free pair of slots that "fits" the units output?

Delaying one output seems to be the better solution.

-- 
 Michael "Tired" Riepe <Michael.Riepe@stud.uni-hannover.de>
 "All I wanna do is have a little fun before I die"
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