Re: Rep:Re: [f-cpu] parse VHDL code to create documentation

[Michael Strothjohann <strothjohann@rheinahrcampus.de>]

> >Are you interested ?
> 
> I'm interrested to use it, not reeally to write it.(i
> will probably write a test bench generator)

ok, you are not realy interested to start from the ground
writing your own tool. your decision.  ( btw: using bison, it is not
hard to
write a parser, it is nearly a copy from the VHDL-language-description;
i came from verilog and it was a good help for me to write
the parser learning the vhdl-details). 
You are looking for a ready-to-use-parer incl. source code. You can
found some under : http://www.vhdl.org/complang.vhdl/FAQ3.html
The one written by Andreas Dangberg is in java and it is with
some graphical output. ( i think, not the output you are asking for,
as i remember his output is like a structural tree of the vhdl code.
please check it. )  
 
> >not so easy to write the FSM-VHDL->graphic converter
> 
> For me, there one way to write simple FSM (no stack,
> synchronous) correclty (as generated by renoir : 3
> processes, one clocked, one to generate the next
> state, one to generate the output). 

if you are shure to use this simle partition 
in all further(!) cases, and don't use hir fsms,
or some of the other addons, then it is realy a short homework
to write an extension to any (special:the mentioned) VHDL-parser
to convert the vhdl-netlist ( generated by the parser ) 
to a graphical description. Now it comes to 'automatic' Bubble-layout : 
if you are using java, see the sun demo : GraphLayout in the
demo/applets-dir of there developer distribution.   

> The other implementation aren't good, 
> or are a mixe of fsm and data path.
> nicO

my opinion: please have in mind: fsms with more then 10-15 states
are easier to work with when there is a textural (vhdl)-description,
your display is probab not able to show all states of your fsm at once. 

michael strothjohann
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