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Rep:Re: [f-cpu] parse VHDL code to create documentation



-----Message d'origine-----
De: Michael Strothjohann
<strothjohann@rheinahrcampus.de>
A: f-cpu@seul.org
Date: 27/06/01
Objet: Re: [f-cpu] parse VHDL code to create
documentation

>Are you interested ?   

I'm interrested to use it, not reeally to write it.(i
will probably write a test bench generator)

>not so easy to write the FSM-VHDL->graphic converter


For me, there one way to write simple FSM (no stack,
synchronous) correclty (as generated by renoir : 3
processes, one clocked, one to generate the next
state, one to generate the output). The other
implementation aren't good, or are a mixe of fsm and
data path.

>michael strothjohann
nicO

 
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