[f-cpu] Register bank

[<nicolas.boulay@ifrance.com>]

An other think about register :

Todays we need 3 read port and 2 writes port, but the
instruction are 2r1w. So i suggest to implement
access twice the size of the register then use a
multiplexor, and the access to the *(reg+1) are only
possible with even register number. So we reduice the
number of register port, with just one more little
constraint.

We can also introduice an other trick. A study from
sun said that 50% of the operand come from the bypass
net. So we need a bypass net. So need control to
manage bypass net and that's not so simple. What
about mapping each level of the pipeline in the
register bank ?

I know, Whygee, we have different unit latency. But
in fact, that's isn't new at all, sorry. To manage
coherency they just buffer the result in the 
pipeline to the longuest path. So there is always one
output per cycle. So with static scheduling, we could
avoid to use of 'true' register. 

A read to this 'register' are easy to understand, but
what about a write. We could imagine just that the
data is lost or what ever you want.

nicO

 
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