Re: [f-cpu] branch system

[Thilo.Reichelt@t-online.de (Reichelt)]

nicolas.boulay@ifrance.com schrieb:

>
> So, i have the idea to put the usual 2 bit of the
> prediction of the branch inside the instruction word.
> So we need a prefetch, a -1 pipeline stage which
> prepare the instruction flow using the branch
> prediction mecanism. In case of wrong prediction,
> this 2 bit are change in the Icache. No need for a
> specific memory, and you could try to introduice
> static prediction. So further call to the instruction
> behave differently. The problem is to have the jump
> address. But to shorten the pipeline we only accept
> direct register access. So the addresse is compute
> before. 
>
Long time ago, there was an idea use to the rightmost 2 bits of the jump address 
as prediction bits.
Since instructions are aligned to 4-byte-boundaries the two rightmost bits are 
zero by definition. These bits are free to store prediction bits. The compiler 
has a harder job, because the prediction bits are not in the jump instruction, 
but in the addresses in a jump table. The idea was even to change the bits 
according to the last branch taken or not. 
This has the strange consequence that a jump (Reg13) changes the content of 
Reg13. You can use it for jumping again, but you can not read the first byte of 
the instruction word via Reg13. 
But that is just strange, not a real problem. The only use I can imagine 
for doing that (reading bytes which were a branch target before) is 
self-modifing code, and that is considered EVIL anyhow. All well-behaved 
programs know to keep the data pointers and code pointers separate.    


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