[f-cpu] branch system

[<nicolas.boulay@ifrance.com>]

Last day, i think about branchs. How to loose fewer
cycle as possible. Branch prediction are the best way
to do it. We need a udge cache to put the adress.
Pentuim use 512 entries, with 2 instruction in it.
SH5, decode the first 2 stage of the pipeline and
buffer the result to garantit zero wait state. But
that's a udge amount of silicium ! 

So, i have the idea to put the usual 2 bit of the
prediction of the branch inside the instruction word.
So we need a prefetch, a -1 pipeline stage which
prepare the instruction flow using the branch
prediction mecanism. In case of wrong prediction,
this 2 bit are change in the Icache. No need for a
specific memory, and you could try to introduice
static prediction. So further call to the instruction
behave differently. The problem is to have the jump
address. But to shorten the pipeline we only accept
direct register access. So the addresse is compute
before. 

In that case, we need a new branch instruction PC
relative. But for short jump, to reduice the size of
the adder, 10 bit will be great. So the CDP is wider.
So a wrong prediction cost more.

That's a vicious circle. Then i remenber that 
compatibility is what produice actual udge heavy
beast as intel processor. 

Whygee kill the delayed branch trick. It's not
possible in superscalar mode and much difficult in
case of longer pipeline. I know that.

BUT, we don't need the short lenght branch (CDP
shorter), we don't need fluching the pipeline (less
control glue), we don't need branch prediction (a lot
less glue, and don't need any more a port access to
the Icache), we never lossing one cycle in all case !

It was what is the simpliest to implement, and the
more efficient. So...

nicO

 
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