Re: [f-cpu] manual update

[nico <nicolas.boulay@ifrance.com>]

Yann Guidon a écrit :
> 
> hi,
> 
> Michael Riepe wrote:
> 
> > On Thu, Jun 06, 2002 at 12:50:05PM +0000, Nicolas Boulay wrote:
> >> p195 Chapter 3
> > [...]
> >> - We can't impose that more than 2 register can't point on the same
> >> cache line. What happen with :
> > Why should we do that? Every register may point everywhere.
> 
> physically, yes.
> However there might be a HW limitation for the first versions.
> The code will work but might have some thrashing (one or
> two cycles of penalty per access where several pointers
> point to the same line).
> 
> Please give me some time to explain that.
> i started to answer nicO's mail but haven't
> finished yet. it's not a simple thing to explain.
> 

In fact, it's very easy to explain. But It's not the strong point of
Whygee ;D

To speed up things, register adress are used as an inputs inside  kind
of cache and return the content of a cache line (or more) pointed by the
content of the register. So we bypass the register read and we can
immediately acceded to the content of the memory before having read the
register bank. To verify the integrity, we check the real adresse with
the adress read in the register.

This memory could react as a caches. But i think that a 64 registers
adresse isn't so much and we can use a memory instead of a cache system
(with 8 lines instead of 64).

The problem are alias what's up if 2 registers write on the same
location thought 2 differents pointers ? This line are no more up to
date (this unit are the LSU, if i have a good mem).

Whygee seems to have found an idea to handel that with 2 pointers. I
personnaly beleive that's to much glue logic.

This mecanism could be only used for code because it's "mostly" read
only, so there no alias problem. But for data, i don't know. I have
proposed instead of using the register adress to use the stream number
of the load&store instructions.

That's the main purpose of the stream : differentiate data stream. 

nicO

> WHYGEE
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