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Re: [f-cpu] Status quo

On 3/28/2015 5:39 PM, whygee@xxxxxxxxx wrote:

Hi Ben,



but then you have to mix two kinds of results.
selecting from two different carry chains adds gates and delay,
either as a fanout tree or a fanin tree,
in the most critical datapath (the add unit).


Excess 3 uses the 4 bit carry out to add +3 or -3 to correct the digit.
This adjust could be added later in the pipeline, because the freq of
decimal math is rare, compared to say address calculations.
What I am thinking of are the new standards that now need BCD math.


Streamlining is fine, but regardless cache memory not raw gate speed
is the limiting factor today.

It depends, in ASIC probably, however what are the odds one of us can
go to a fundry soon ?


From what little I have seen is that you are limited to 3 input gates
with modern CMOS technologies.


For now we can use FPGA. I stick to the ProASIC3 family because the
gates are very similar to ASIC precharacterised gates and it exposes the
inherent
latencies better than the competitors.
In FPGA the speed ratio between SRAM and logic is a bit different.
SRAM blocks are already optimised.

Anyway, in both cases, the real bottleneck is the I/O pins and
the external memory interface... Fortunately the latest FPGA
generations have decent DDR2 or DDR3 interfaces. The Igloo2 is
a pretty nice chip that supports this and I have already planned
to use it, along with ProASIC3 for smaller, cheaper designs.


That is the main thing. Here I get play with TTL techology
from the early 70's. 8K word was a big as you got with out going
to another rack of memory.


I'm fortunate to be able to use, create and develop technologies for my
work with the ultimate goal to reuse them for this project :-)
yg
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Ben.



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