Re: [f-cpu] Shifter, like during the good old days ;p

[nicO <nicolas.boulay@ifrance.com>]

I have just learn something todays ;p (But how do you create the diff
file ?)

First :) Something goes wrong !
------
Warning: Variable 'Bitrev' is being read 
        in routine Shuffle64 line 298 in file
'/home/profelec/nboulay/perso/fcpu/shl/fcpu-shl-mr-20011102/eu_shl/shuffle64.vhdl', 
        but is not in the process sensitivity list of the block which
begins 
        there.   (HDL-179)
---------
Euuuuh ????:

check_design
Warning: In design 'Shuffle64', port 'Clk' is not connected to any nets.
(LINT-28)
Warning: In design 'Shuffle64', port 'Rst' is not connected to any nets.
(LINT-28)
Warning: In design 'Shuffle64', port 'En' is not connected to any nets.
(LINT-28)
1
----

I wait tomorow for the end of synthesys.

nicO

Michael Riepe a écrit :
> 
> On Sat, Nov 03, 2001 at 05:04:42PM -0500, nicO wrote:
> > ------
> > elaborate Shuffle64 -gate_clock
> > Error: Can't determine type of aggregate or concat
> >         in routine rotate line 181 in file
> > '/home/profelec/nboulay/perso/fcpu/shl/fcpu-shl-mr-20
> > 011102/eu_shl/shuffle64.vhdl'
> 
> *argh* Synopsys caught me again :(
> Here's a quick-and-dirty fix that should work:
> 
> ======= chainsaw =======
> Index: f-cpu/eu_shl/shuffle64.vhdl
> ===================================================================
> RCS file: /home/michael/cvsroot/f-cpu/eu_shl/shuffle64.vhdl,v
> retrieving revision 1.8
> diff -u -r1.8 shuffle64.vhdl
> --- shuffle64.vhdl      2001/11/02 20:07:45     1.8
> +++ shuffle64.vhdl      2001/11/03 17:18:08
> @@ -148,6 +148,7 @@
>                 alias uu : std_ulogic_vector(U'length-1 downto 0) is U;
>                 variable yy : std_ulogic_vector(w-1 downto 0);
>                 variable xx : std_ulogic_vector(w/2-1 downto 0);
> +               variable xt : std_ulogic_vector(w/2-1 downto 0);
>                 variable cc : std_ulogic_vector(5 downto 0);
>                 variable t : std_ulogic;
>         begin
> @@ -178,7 +179,8 @@
>                                 xx := bit_reverse(xx);
>                         end if;
>                         if i >= 3 then
> -                               xx := xx and (w/2-1 downto 0 => uu(i-3));
> +                               xt := (others => uu(i-3));
> +                               xx := xx and xt;
>                         end if;
>                         yy := omega_1(yy, xx);
>                 end loop;
> ======= chainsaw =======
> 
> --
>  Michael "Tired" Riepe <Michael.Riepe@stud.uni-hannover.de>
>  "All I wanna do is have a little fun before I die"
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