Re: [f-cpu] whygee's Nth slaughtered ROP2 version

[Josh Fender <fender@ecf.utoronto.ca>]

On Sun, 25 Nov 2001, Michael Riepe wrote:

> On Sun, Nov 25, 2001 at 03:47:12AM +0100, Yann Guidon wrote:
> [...]
> > >  Maybe a less useful, but more interesting, fact is
> > > that when placed in a Xilinx Virtex grade 6 chip it runs at 85MHz.
> > the little problem is that i don't know whether it's fas or slow.
> 
> I guess 85 MHz in an FPGA is not bad (depends on the FPGA type, of
> course).  I'd like to see the numbers for the add, mul and shl units,
> too (for the same target, as far as possible -- the multiplier probably
> won't fit, but the other EUs should).

  If someone was to provide a working set of units, I could try them all
out.  I could try the multiplier unit aswell as the FPGAs I am using are
relatively large (approximately 40000 Look up tables/ Flip Flops units).
It might not fit but its always worth a try.

  I am curious about the target of the F-CPU.  A lot of the design seems
to be oriented towards FPGAs and their four input logic, yet the
multiplier most certainly is not.  So my question simply is:  What is the
current target platform for the first F-CPU?  Is it an FPGA or a custom
chip.

- Josh


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