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Re: [f-cpu] optional SRB

On Mon, Nov 25, 2002 at 06:45:25PM +0100, Antoine wrote:
> For IRQ/trap handlers you probably also need :
> - a SR_PC which automatically holds the PC value just before the
> context switch

Yes, definitely.

> - a set of temporary SRs with no other purpose than holding
> temporary values (let's say SR_TMP0 ... SR_TMP3). This because
> you need to save some registers before even the register save
> pointer is set up (at the very least you need to save the registe
> that will contain the register save pointer :-))

We need at least one of them, yes.

> - an instruction which takes SR_PC and loads it into the PC.
> The instruction that returns from an IRQ/trap handler cannot
> use a general-purpose register, because the interrupted
> thread (or whatever you call it) needs to have all its registers
> untouched. This instruction could be called "reti" (return from
> interrupt).

It already exists, and is called `rfe'.

> - an EI instruction to re-enable interrupts. Indeed, when a IRQ/trap
> is launched, interruptions should be automatically disabled by the
> CPU, because the very beginning of the handler will not be reentrant ;
> then you will re-enable them after the non-reentrant part is finished
> (which probably means when all registers are successfully saved).
> The DI instruction is optional.

This could be handled via SRs. E.g. interrupts could be re-enabled
when SR_PC is read for the first time, or when `rfe' is executed,
whichever happens first.

 Michael "Tired" Riepe <Michael.Riepe@stud.uni-hannover.de>
 "All I wanna do is have a little fun before I die"
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