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encore une couche (was: Re: [f-cpu] License issues GPL/LGPL and Juergen Goeritz' SoC)
btw i bought Ashenden VHDL book today
and i got the CD with the Cadence download from
our french friend Olivier. Looks like i'm not going
to sleep before next summer...
ok, back to the discussion :-)
> Michael Riepe a écrit :
> > On Sat, Sep 15, 2001 at 01:59:48PM -0400, nicO wrote:
> > [...]
> > > > > Yep, if they can earn money, and there work will not be stolen as
> > > > > explain by Michael.
> > > > this means that we are in the case where the company's "central activity"
> > > > is not making CPUs but using them.
> > > ??? It's evident : how many compagny make cpu ? Few dosen ? How many use
> > > them ? thousand ?
> > I guess the term `use' has to be clarified, too. IMHO, `using the F-CPU'
> > can only mean `running the processor' -- no matter how it's implemented.
> > This kind of use should not be restricted by us at all, and must not be
> > restricted by others, in order to maintain users' freedom. This is what
> > the GPL means when it says `you may use the program freely'.
> That's true. But GPL means that the compagny should release it's own
> code, too. Imagine an fft bloc to make fast encoding for a communication
> system. 12 Months of work.
Ray Andraka (comp.fpga, comp.dsp...) developped a 16-tap Winograd complex FFT
in 6 man/month. i don't remember the price for the bitstream licence or the source,
but he was kind enough to send me the original transformation matrices
he got from a book. i think that you (nicO) have seen the 3 matrices
at the Sous-Bock. he did not send me the result of his work, but the beginning
If Ray wants to integrate his core _inside_ the f-cpu core, he HAS to divulgue the
source. However i believe he's smart enough to find a work-around, like mapping
his I/O in uncachable memory so you access the functionality outside of the core.
I believe that some people are smart, yes :-) at least enough to find solutions
> If they want to use fcpu, they should release under the GPL code. Great
> for us !
release what ? the modified source.
> But for them, do they want to take the risk that there opponent
> develop there chip with there work ? They just need to copy there work
> without adding any value.
> I stay at the VHDL level. For my part, i prefer that they use fcpu
> instead of an ARM. I prefer that they debug a fcpu rather than we try to
> keep another design because they choose to use an fcpu.
btw, do you access a synthesiser currently ?
Accessing Cadence ncsim is cool and sexy, but it's pretty useless if
our source code doesn't synthesise... I'll start at Jussieu on the 28th
and i'll have some ressources, but not everything. Other's (ie: Kim)
help will still be precious.
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