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Re: [f-cpu] Something new to play with :)



On Mon, Sep 24, 2001 at 12:59:39PM +0200, Yann Guidon wrote:
> hi !
> 
> Kim Enkovaara wrote:
> > On Sat, 22 Sep 2001, Michael Riepe wrote:
> > 
> > > Can someone (nico? Kim?) please try to synthesize it?  I would like to
> > > hear how fast it runs.
> > 
> > We should take some chip as a reference and always synthesize for it.
> > Otherwise the results are not comparable. But to even get some feeling I
> > synthesized this block to Virte2 (XCV2V1000-BG575-6) and got following
> > results:
> > 
> > Speed: 66MHz (optimized for speed, no special tricks)
> wow :-)
> what is the fastest thing you have synthesised for this device ?

That's nothing -- the multiplier was faster :)
But I'm quite satisfied with that result.

> > Utilization: 30%
> wow :-/
> How big is it btw ?

The multiplier also took something like 30%.  The SHL EU is very
space-consuming...

> > btw. the muxes are quite huge :) FPGA architectures usually have some
> > problems with complex multiplexer structures.
> 
> this is why i prefered to use 4-in muxes :-)

Too big for most FPGAs.  All you can do with 4-input cells is a 2:1 mux.

> Can you track where the critical datapaths are located ?

I guess it's in the control logic for stage 2.

-- 
 Michael "Tired" Riepe <Michael.Riepe@stud.uni-hannover.de>
 "All I wanna do is have a little fun before I die"
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