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Re: [f-cpu] Bit Shuffler (Take 2)

On Fri, Sep 28, 2001 at 07:34:37PM -0400, nicO wrote:
> Should i suggest to try to make the mul with mul 8*8 entity ? Synplicity
> use very high level optimising schem (it doesn't try to simplify at the
> gate level but at the structure level, that's why it's faster and more
> performant than the other fpga compiler). Our [michael;p] SIMD 64 bits
> mul should be quicker with basic 8 bits bloc. But this could be only
> true with fpga.

The multiplier was fast enough -- more than 100 MHz (in an FPGA) --
and an 8x8 architecture would need more stages (my first version hat 8x8
building blocks, and 9 or 10 stages, while the current one has only 6).
I don't worry about that, but the shifter gives me headaches.

 Michael "Tired" Riepe <Michael.Riepe@stud.uni-hannover.de>
 "All I wanna do is have a little fun before I die"
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