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Re: [f-cpu] Bit Shuffler (Take 2)

On Fri, 28 Sep 2001, nicO wrote:

> Should i suggest to try to make the mul with mul 8*8 entity ? Synplicity
> use very high level optimising schem (it doesn't try to simplify at the
> gate level but at the structure level, that's why it's faster and more

Synplify usually likes as high level descriptions as possible. But I think
that optimizing for speed at this stage is not wise thing to do. First you
need a working chip and testbenches around it. After that it is easy to
recode some blocks for ASIC and FPGA for example. Of course it is
necessary to check that the blocks are synthesizable and reasonable sized
and the speed is reasonable. But targeting for maximal speed comes later.

Mr. Kim Enkovaara   | kim.enkovaara@iki.fi | Microelectronic Riemannian
Vasamatie 1 C 16    | IRC: embo            | curved-space fault in
02630 Espoo         |                      | write-only file system

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