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Re: [f-cpu] Bit Shuffler (Take 2)


Kim Enkovaara wrote:
> On Fri, 28 Sep 2001, nicO wrote:
> > Should i suggest to try to make the mul with mul 8*8 entity ? Synplicity
> > use very high level optimising schem (it doesn't try to simplify at the
> > gate level but at the structure level, that's why it's faster and more
> Synplify usually likes as high level descriptions as possible. But I think
> that optimizing for speed at this stage is not wise thing to do.
how do you tell Synplify to pipeline the multiplier ? and how do you instruct it
to provide partial results ?

> First you need a working chip and testbenches around it. After that it is easy to
> recode some blocks for ASIC and FPGA for example.
it won't be easy if we did not foresee the necessary requirements.

> Of course it is
> necessary to check that the blocks are synthesizable and reasonable sized
> and the speed is reasonable. But targeting for maximal speed comes later.
Today, now that i see that i can code something, i wonder : what is the best
way to write stuff so it runs as fast as possible. I know that if i start to
write VHDL "the usual way", the result might be disapointing. If a large part
of the CPU is designed this way, it won't hold its promise. People will work
on underefficient designs and it will be too late. This is particularly
worrying in the control path (scheduler). I trust Michael for the rest.

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