Re: gEDA-user: HELP with Icarus Verilog, 0.7!

["Samuel A. Falvo II" <sam.falvo@falvotech.com>]

On Tuesday 06 April 2004 04:13 pm, Mike Jarabek wrote:
> The same condition is still there, it has just moved to the address
> inputs instead of the enable signals.  It's something of a bad idea to
> use the clock to qualify signals, especially if this is a synchronous
> design anyhow.

I'll get to the other experiment you posted above, once I get back from 
work.

However, your advice is contradictory to real-world experience with the 
6502-series of processors, where qualification of bus signals to the 
system clock is not only preferred, but often the only way to achieve 
such qualification.  I refuse to believe it is a "bad idea."  Maybe a 
bad idea in a certain context, but certainly not for all cases.  And you 
just can't get any more synchronous than the 6502 bus.

In fact, the 65816 has far more stringent synchronous constraints, as it 
places the upper 8 bits of the address bus (bits 16..23) on the data bus 
while the clock is low, with the expectation that they'll be latched at 
that time, or on the rising edge of the clock.

There are 6502/65816 systems in existance that can go up to and often 
beyond 20MHz.  So it can't be all that bad a thing to do.

--
Samuel A. Falvo II