Re: gEDA-user: Verilog and three-state bus help?

["Samuel A. Falvo II" <sam.falvo@falvotech.com>]

On Tuesday 06 April 2004 03:53 pm, John Sheahan wrote:
> in general, tristate busses within a chip are in my opinion evil and
> should be avoided.

This is irrelavent; I would still like to model a complete *system*, as 
it will appear on the finished printed circuit board.  Obviously, not 
all components will reside on a single chip.

> If you have to do this, I'd suggest you use a wrapper that separates
> the bus into 2 directions, and
> just resolve the busses there, once.

Of course.  That's precisely what I tried to do.  Isn't that clear from 
my assignment to DB from DBout based on the status of the "rd" signal?

> I suspect you also need to review the difference between wires and
> registers,

Comments like this are unhelpful, and have a very condescending tone to 
it.  What, exactly, should I review?  Give me a direction to go forward 
in; don't just tell me I'm lost in a desert.  Trust me, I already know 
the latter.

I can assure you that I've tried *numerous* methods to attain my goal, 
including use of various register types, various net types, and nothing 
would work.  Otherwise, I wouldn't have asked on the mailing list, 
obviously.

--
Samuel A. Falvo II