Re: gEDA-user: Verilog and three-state bus help?

[John Sheahan <jrsheahan@optushome.com.au>]

Samuel A. Falvo II wrote:

> I'm wondering if anyone saw my last message relating to Verilog and how 
> to model a three-state bus in Icarus?
>
> --
> Samuel A. Falvo II
>  
your issues were not icarus related - just verilog.

in general, tristate busses within a chip are in my opinion evil and 
should be avoided.

If you have to do this, I'd suggest you use a wrapper that separates the 
bus into 2 directions, and
just resolve the busses there, once.
I suspect you also need to review the difference between wires and 
registers,
from your example.
john