Re: gEDA-user: Assertion based verification using VCD and VHDL

[John Sheahan <jrsheahan@optushome.com.au>]

Stuart Brorson wrote:

> Hi --
>
>  
> > I am trying to locate an open-source tool chain that I can
> > use for assertion based verification of a design. 
> >    
> [snip]
>  
> > I extract SPICE for the design and run simulations
> > of the design in SPICE.  I then take the raw output from
> > the SPICE run and generate a VCD (value change dump) file.
> >    
> Interesting.  What tool do you use to get from .raw to a .vcd file?    
>  
> > What I would really like to do is to be able to use my VHDL
> > test bench to verify my SPICE simulation to make sure that
> > there were no errors introduced during the layout phase.  I
> > could do this by running my VHDL test bench against the SPICE
> > results.  It seems that the one piece that I am missing is
> > a 'vcd2vhdl' type program that could take a VCD file and generate
> > a VHDL entity/architecture that I could simulate.  In theory
> > the same signals would exist in both my VCD and VHDL designs and
> > therefore my assertions could be applied to the converted VCD
> > entity/architecture.
> >
> > So, does anyone know of a 'vcd2vhdl' type tool?  It seems like
> > a basic tool would be pretty simple to develop, but why invent
> > the wheel if I don't have to.
> >    
> Ummm. . .  I can't imagine how the tool would work, unless it just
> translates the .vcd file to a series of "signal <= value AFTER time"
> statements.  Synthesizing logic from a bunch of waveforms seems to be
> a difficult task, if you ask me.
>
>  
> > Finally, is there a better way to verify the operation of a
> > digital circuit simulation done using SPICE?
> >    
> Not that I am aware of, unless you want to shell out $100K for a
> commercial mixed-signal design package.  The gEDA project has gotten a
> couple of expressions of interest from folks interested in using it
> for mixed-signal chip design.  Peter Kaiser has a website with one or
> two interesting tidbits:
>
> http://www.easy-asic.de/
>
> He has apparently used gEDA & spice-sdb for mixed-signal ASIC design.
> However, his page has nothing which directly answers your
> question. You might try e-mailing him using the addr on his page.   
> Finally, since there is such interest in using gEDA for mixed-signal
> design, my question to you is: How much is a free-standing vcd2vhdl
> tool worth to you and your company?  It seems to me that such a tool
> would be of some interest to all kinds of ASIC designers . . . . . 
> Stuart
>
>  
Seems to me that writing a behavioual model in verilog/vhdl, simulating 
that (in the hdl),
and comparing the vcd from the hdl to the spice derived vcd might be a 
lot simpler,
and of more general use.

john