RE: gEDA-user: Verilog and three-state bus help?

["Jason Doege" <jdoege@inovys.com>]

Hi Samuel,

Whenever I've modeled tristate busses, it's always been something like
this:

Module parentmod ();
wire three_state_wire;
wire control1, control2, data1, data2;
...
three_state_driver tsdi1 ( three_state_wire, control1, data1 );
three_state_driver tsdi2 ( three_state_wire, control2, data2 );
endmodule

module three_state_driver ( port, control, data );
input control, data;
inout port;

assign port = control ? data : 1'bz;

endmodule

Design rules suggest that at the chip level, control inputs to bus
drivers should be mutually exclusive. However, there is often a lot of
push-back from designers on this matter. At the system level, of course,
mutual exclusivity is impractical.

As a practical matter, most folks set up state machines at each end of
the bus that assure mutual exclusivity in operation through sequential
behavior. However, in illegal states they could cause contention. This
would normally not be a problem except that I am a DFT engineer and
delight in putting devices into all kinds of illegal states for the
legitimate purposes of test.

Consequently, I tend to mandate unidirectional busses as a design rule.
When it is proven the design can not live without bidirectional busses,
then I let them in and we figure out how to make them safe for test
purposes.

Mr. Sheahan was not being condescending, just a little ignorant (not a
pejorative in this case.) He did not realize you were speaking about
system level design, and, based on the levels of your questions, which
are quite remedial, assumed that this would be useful information to
you.

Best regards,
Jason

--
Jason Doege          | email: jdoege@inovys.com
Inovys Corporation   | phone: +1 512 422 9483
11417 Carnelian Dr.  | fax:   +1 925 924 9118
Austin, TX 78739     | page:  5124229483@tmomail.net


-----Original Message-----
From: owner-geda-user@seul.org [mailto:owner-geda-user@seul.org] On
Behalf Of Samuel A. Falvo II
Sent: Tuesday, April 06, 2004 6:03 PM
To: geda-user@seul.org
Subject: Re: gEDA-user: Verilog and three-state bus help?

On Tuesday 06 April 2004 03:53 pm, John Sheahan wrote:
> in general, tristate busses within a chip are in my opinion evil and
> should be avoided.

This is irrelavent; I would still like to model a complete *system*, as 
it will appear on the finished printed circuit board.  Obviously, not 
all components will reside on a single chip.

> If you have to do this, I'd suggest you use a wrapper that separates
> the bus into 2 directions, and
> just resolve the busses there, once.

Of course.  That's precisely what I tried to do.  Isn't that clear from 
my assignment to DB from DBout based on the status of the "rd" signal?

> I suspect you also need to review the difference between wires and
> registers,

Comments like this are unhelpful, and have a very condescending tone to 
it.  What, exactly, should I review?  Give me a direction to go forward 
in; don't just tell me I'm lost in a desert.  Trust me, I already know 
the latter.

I can assure you that I've tried *numerous* methods to attain my goal, 
including use of various register types, various net types, and nothing 
would work.  Otherwise, I wouldn't have asked on the mailing list, 
obviously.

--
Samuel A. Falvo II