Re: gEDA-user: [PCB] Bug? Silk tracks clear poly on file reload

[Dave N6NZ <n6nz@xxxxxxxx>]

Ben Jackson wrote:
> On Wed, Apr 02, 2008 at 10:44:01AM -0800, Dave N6NZ wrote:
>>> Can you send a sample file?  Maybe the real problem is that the line is
>>> not on the silk layer after a reload.
>> No, the tracks stay on the silk layer, like they should.  Somehow the 
>> plow poly check seems to get missed.
> 
> I bet it's not on the silk layer at load time.  There was a bug where
> loading boards were cleared in the context of the previous board's layer
> stack.  I fixed it a while ago.  I think if you load, see the problem,
> and then immediately 'revert' (to reload) it might go away.  The second
> load would use the right layer stack.  

OK.  That seems to fix the small test case that I sent you.  I'll try 
that on my larger design.

> If that's true, current CVS should
> also fix it.

OK.  I should rebuild anyway.

Thanks,
   Dave

> 


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