Re: gEDA-user: [pcb] merging layers and pasting

[John Griessen <john@xxxxxxxxxxxxxx>]

DJ Delorie wrote:
the layers are merged 1..N in
> order, without regard for component/solder side or groups.  I'm
> thinking this is bad, 

[jg]Yep.  We can do better and make pcb/gerbv real speed tools.

> First, if there's a single layer in the solder or component group, and
> the current board also has a single layer there, we match those up.
> 
> For non-component-solder layers, we look for existing layers with the
> same name.  If it's a one-layer-per-group case, we just match them up.
> 
> In cases where there's multiple layers in a group, it gets
> interesting.  We may get lucky and be able to match up c/s layers by
> process of elimination or by matching names, likewise with other
> groups.
> 
> We can correlate outline layers of course.
[jg] Because there's only one per design?  Mmmm... I can imagine a gerbv-2-pcb
import with odd names where even that did not match...


> 
> In the case where we can't figure out what to do, I think a pop-up
> dialog would be appropriate (the HID has a way to do this already).

Sure...
> It would list all the layers that can't be automatically correlated,
> with a multi-select box of potential layers to correlate them to.  We
> may be able to group these by component/inner/solder, so that an
> uncorrelated component group can be matched with existing component
> groups, etc.
> 
> We may also need the option to correlate multiple input layers to a
> single layer - i.e. a generic "merge layers" option, which might be
> useful as a standalone action too.

Sounds great, just kinda hard to code...
> 
> If all else fails, an option to create a new layer for an uncorrelated
> input layer.

[jg]It would be fine to just stop and allow user to create a new layer
without auto-dialog based code.  What would be good is to create a
pcb_panel_project file (and do gerbv the same way with a matching format
gerbv_panel_project file), that lists the layers for the panel and how any
individual imported boards are to be matched up with those layers.
That way the project layers could even be renamed to fit with a fab shops
preferences for clear communication with them.  With this approach,
original separate named layers that are intended to be merged could be left separate,
yet a merged layer for fab purpose could be created and contain the merge
of the original layers, or not.

Here's a likely file format, where comma separated lists get additively merged, # lines are comments and ignored
and different boards are just merged by having their left side entries be the same:


#board one
top_cu_1oz_bloat0003 : component
top_silk :   component-silk

#board two
top_cu_1oz_bloat0003 : component_PWR, component_SIG
top_silk :   silk

#board three
top_cu_1oz_bloat0003 : component_PWR
top_silk :   logo_orange_silk
top_silk :   silk_white


If you got this far and came across one of my boards
with insulator layer, the project file would be updated to a point where you could stop and
think, and create another layer for the left column of the project, and continue with no lost
work.  Every GUI choice should cause a project file write is my preference.
And likewise, every GUI choice should read the project file and compare program state and
offer ways to sync state with the project file...

John Griessen
-- 
Ecosensory   Austin TX


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