Re: gEDA-user: Open VHDL Simulators?

[Hagen SANKOWSKI <hsank@xxxxxxxxxxxxxxxxxxxx>]

Hello.

Am 25.04.2008 um 23:04 schrieb Stephen Williams:

>
> As you know, this year's Icarus Verilog GSoC candidate is working
> on a VHDL code generator back-end for Icarus Verilog. Hooray!
> But suddenly the obvious question comes up, "How are we going to
> run these generated files?" I'm here looking for suggestions.
>
> Has anybody here used ghdl? freehdl? Relative merits? Which is
> most active? The most portable? Easiest to use?
>
> It just seems like ghdl has the most activity associated with it,
> but FreeHDL doesn't look completely dead either. So what to choose?

Well, I used ghdl some yeas back for a small project and was surprised  
of the instability. The simulation failed with obivous error messages.  
For ghdl I see the pitfall of design at close relationship between  
ghdl and a dedicated (old fashioned) version of GCC. Freehdl doesn't  
compile on my box.

As a freelancer now 10 years in business I work nearly on a every day  
basis with *both* languages, Verilog HDL and VHDL. In general, I see  
two trends.
First, the serious and bigger the SoC design, the often companies  
probably use Verilog instead of VHDL. So the offer with language  
knowledge for Verilog or VHDL is even a good indication of ambitions.
Second, with SystemVerilog and all the released sources for the Sparcs  
and PowerPC the Verilog camp overruns the more european and academic  
design villages. For me the development of VHDL slows down in general  
while SystemVerilog eats the market for dedicated Verification  
languages.

Mostly bad VHDL design goes to FPGA, good Verilog design goes to ASICs.

So please Steve, keep your attention on Verilog, 'a cobbler should  
stick to his last'. And, btw. you did a great job with icarus :-)  
Thanks! If you want support VHDL, than be aware that the VHDL language  
is more hugh than Verilog with even millions of pitfalls and ways to  
describe one behavior. ghdl and freehdl are light years away from  
quality of icarus. Your code generator at the moment supports EDIF,  
right? So why you don't use Verilog itself again? This will be a good  
starting point for netlist-based timing simulations with rising SDF  
support. If you are in need of the Verilog to VHDL translation, keep  
an eye on this dedicated tools, they works fine.  And keep the Unix  
philosophy, one tool should do one thing, but this one great.
If there is one Verilog lover or programmer with spare time, I still  
miss a better quality for Coverage and even a Lint tool for Verilog..

Regards
hsank



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