Re: gEDA-user: Open VHDL Simulators?

[Hagen SANKOWSKI <hsank@xxxxxxxxxxxxxxxxxxxx>]

Hello.

Am 29.04.2008 um 01:23 schrieb Stephen Williams:

> Attila Kinali wrote:
>> On Sat, 26 Apr 2008 09:22:17 +0200
>> Hagen SANKOWSKI <hsank-GMWn+aNOpombZ5jwVEtKn2D2FQJk+8+b@xxxxxxxxxxxxxxxx 
>> > wrote:
>
>>> Mostly bad VHDL design goes to FPGA, good Verilog design goes to  
>>> ASICs.
>>
>> Uhm... I don't think i have to comment on something uneducated
>> like this, do i?
>
> Right, let's please not fall into this pit. I was hoping the mud
> would dry up and blow away.

Sorry, I don't want to put up a pit. Just a moody observation over the  
years...

Regards,
hsank


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