Re: gEDA-user: Open VHDL Simulators?

[Stephen Williams <steve@xxxxxxxxxx>]

Attila Kinali wrote:
> On Sat, 26 Apr 2008 09:22:17 +0200
> Hagen SANKOWSKI <hsank-GMWn+aNOpombZ5jwVEtKn2D2FQJk+8+b@xxxxxxxxxxxxxxxx> wrote:

>> Mostly bad VHDL design goes to FPGA, good Verilog design goes to ASICs.
> 
> Uhm... I don't think i have to comment on something uneducated
> like this, do i?

Right, let's please not fall into this pit. I was hoping the mud
would dry up and blow away.

-- 
Steve Williams                "The woods are lovely, dark and deep.
steve at icarus.com           But I have promises to keep,
http://www.icarus.com         and lines to code before I sleep,
http://www.picturel.com       And lines to code before I sleep."


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