Re: gEDA-user: Open VHDL Simulators?

[al davis <ad151@xxxxxxxxxxxxxxxx>]

On Monday 28 April 2008, Stephen Williams wrote:
> >> Mostly bad VHDL design goes to FPGA, good Verilog design
> >> goes to ASICs.
> >
> > Uhm... I don't think i have to comment on something
> > uneducated like this, do i?
>
> Right, let's please not fall into this pit. I was hoping the
> mud would dry up and blow away.

That's one of the reasons for the gnucap language plugins.  The 
simulator core is completely neutral to the language.

The snapshot has Spice, Spectre, and Verilog.  VHDL should be 
easy, and will happen.  This is the structural subset, 
primarily analog.  Behavioral modeling is in plugins.


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