gEDA-user: Open VHDL Simulators?

[Stephen Williams <steve@xxxxxxxxxx>]

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As you know, this year's Icarus Verilog GSoC candidate is working
on a VHDL code generator back-end for Icarus Verilog. Hooray!
But suddenly the obvious question comes up, "How are we going to
run these generated files?" I'm here looking for suggestions.

Has anybody here used ghdl? freehdl? Relative merits? Which is
most active? The most portable? Easiest to use?

It just seems like ghdl has the most activity associated with it,
but FreeHDL doesn't look completely dead either. So what to choose?
- --
Steve Williams                "The woods are lovely, dark and deep.
steve at icarus.com           But I have promises to keep,
http://www.icarus.com         and lines to code before I sleep,
http://www.picturel.com       And lines to code before I sleep."
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