Re: gEDA-user: Open VHDL Simulators?

[Attila Kinali <attila@xxxxxxxxx>]

On Fri, 25 Apr 2008 14:04:38 -0700
Stephen Williams <steve@xxxxxxxxxx> wrote:

> As you know, this year's Icarus Verilog GSoC candidate is working
> on a VHDL code generator back-end for Icarus Verilog. Hooray!
> But suddenly the obvious question comes up, "How are we going to
> run these generated files?" I'm here looking for suggestions.

After rethinking about this. What speaks against adding
a VHDL front-end to Icarus? VHDL and Verilog are feature wise
very similar and those few differences are not that difficult.
As a special benefit it would give us the first OSS simulator
with both VHDL and Verilog support.

There are GPL'ed VHDL yacc/bison definitions out there which
could be reused. And even if not, writing one is just typing
down the definitions.

If someone would take up this task, i'd donate the current
VHDL standards and Ashenden's execellent book on VHDL[1].

			Attila Kinali

[1] http://www.ashenden.com.au/designers-guide/DG.html
-- 
Praised are the Fountains of Shelieth, the silver harp of the waters,
But blest in my name forever this stream that stanched my thirst!
                         -- Deed of Morred


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