gEDA-user: terminators

[DJ Delorie <dj@xxxxxxxxxxx>]

I'm getting close to a final design for my SDRAM board, but I'm
thinking about termination for the SDRAM signals.  This board is
faster than anything else I've done before (133MHz 3.3v).

Updated images here: http://www.delorie.com/electronics/sdram/

The left half of the board (U2 left, U1) runs at 24 MHz, no problem.

The right half of U2, and U2, run at 133MHz.  The longest trace is the
CLK line, at just over 3 inches, the shortest is just under an inch.
However, most of those lines are brought out to logic analyzer
connectors, which may add up to another 1.8 inches (DQ11, for example,
has a combined length of 3.9 inches).

I'm thinking I have enough space to put in some series terminator
packs (8x 0402 SMT) but where and how big?  Is it relative to which
chip is driving the trace?  Should the logic analyzer go on the fast
side or the slow side, or does it matter?  (it's a 500Ms/s analyzer)


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