gEDA-user: iverilog array question

[Patrick Doyle <wpdster@xxxxxxxxx>]

   Hello,
   I am reviewing some Verilog code written by somebody else and run
   through some other Verilog simulation tool, so I know this is a little
   off topic, but I'm not sure where else to ask.
   Anyway, I see code that looks like this:
   reg [7:0] unit_matrix [12:0];
   for (j = 0; j<8; j++)
     for (k=0; k<13; k++)
       unit_matrix[k][j] = some_function(k, j);
   Is it legal to address a particular bit in a memory in this fashion?
   (I thought it wasn't, but I learned verilog a very long time ago and
   am only recently trying to dust off the cobwebs in the verilog cache
   of my brain.)  If it's not legal, would somebody mind quoting me
   chapter and verse as to where that is forbidden?
   You can probably guess where I'm going with this...
   When I run the simulation through iverilog, I get different results
   than when my off-site colleague runs it through whatever verilog tool
   he is using.  If it isn't legal, I can fix up his code and show him
   why he shouldn't code that way.  If it is legal, I can grab Stephen's
   0.9.1 release, see if I get similar results as I'm getting on the
   April-ish snapshot I'm using, and then see what I can do to help fix
   this.
   --wpd


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