Re: gEDA-user: bidirectional delay in verilog?

[DJ Delorie <dj@xxxxxxxxxxx>]

> Are you modeling the FPGA and the DRAM

I have a core SDRAM controller module, and Micron's SDRAM model.  I
have a testbench that runs under Icarus/gtkwave but it's inaccurate as
it doesn't simulate the IOB delays and signal propogation.  When I
model it under Xilinx's simulator, with the pinout connections and
such, it models the IOBs but not the SDRAM, as the SDRAM isn't inside
the FPGA.

So what I'd like to do is get the timing information from ISE and add
it to my icarus testbench, so that icarus can more accurately model
what the whole circuit will do, not just what happens inside the fpga.

Given a 7.5 nS cycle time and ~3nS IOB delays, getting this right is
going to be important.

> You could do something like this:
> 
> | FPGA  | --------- | DRAM |

See http://www.delorie.com/electronics/sdram/


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