gEDA-user: bidirectional delay in verilog?

[DJ Delorie <dj@xxxxxxxxxxx>]

I want to simulate the propogation delay through the fpga IOBs and the
traces on the board.  However, some of the lines are bidirectional
(specifically, the data lines).  It's easy enough (I'm assuming) to
assign a delay on a unidirectional line, but what about bidirectional
lines?


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