gEDA-user: Connecting to vias

["George M. Gallant" <ggallant571@xxxxxxxxxxx>]

   This is a repost from yesterday because I was getting the email digest
   and don't know how to reply via that delivery system.
   I use gschem > netlist > pcb > gerbers to produce boards. Connecting
   a pad to a via that is thermally connected to a polygon on the same
   side
   as the component results in a netlist rat line be generated. Asserting
   the Join function clears the fault. The trace is electrically intact.
   I regularly do "Optimize rats nest" and "Design Rule Checker" to insure
   that the board is complete and has a high level of probability of
   meeting
   the fab house requirements so getting this message is annoying.
   Thanks for the tip on making sure to be centered on the part when
   performing the change sides function.
   Using version 20091103.
   George


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